Effect of Post Metallization Annealing for Alternative Gate Stack Devices

To meet the gate leakage specifications in the International Technology Roadmap for Semiconductors (ITRS), an intensive search is being conducted for alternative gate stack materials. Most of the studies have focused on basic material properties, but very little effort has been directed towards quantifying and understanding the effect of post metallization annealing (PMA) on the electrical properties of the dielectric. In this work, devices were fabricated with a “gate last” process. The gate dielectrics studied included: HfO2 deposited by PVD or MOCVD, as well as Y2O3 and La2O3 deposited by RPECVD and MBE, respectively. Poly-Si gate electrodes were prepared by 600°C LPCVD followed by ion implantation and dopant activation using 900°C 60sec RTA. Device characteristics were measured before and after 20 min 400-450°C forming gas (FG, 10% H2 in N2) annealing. To verify the role of hydrogen in PMA, some devices were annealed in nitrogen only. Capacitance versus voltage (CV), gate leakage current, drain current versus gate voltage, and drain current versus drain voltage were measured. MOSFET device parameter analysis programs with corrections for quantum mechanical effects [1, 2] were used to extract key device parameters: equivalent oxide thickness (EOT), metal-tosemiconductor workfunction, substrate doping, channel mobility as a function of electric field, number of interface scattering charges (Nif), and the interface roughness scattering parameters (L*H product).